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LTC2482 16-Bit ADC with Easy Drive Input Current Cancellation DESCRIPTIO
The LTC(R)2482 combines a 16-bit plus sign No Latency TM analog-to-digital converter with patented Easy DriveTM technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of onchip buffering through automatic cancellation of differential input current. This allows large external source impedances and input signals with rail-to-rail input range to be directly digitized while maintaining exceptional DC accuracy. The LTC2482 allows a wide common mode input range (0V to VCC) independent of the reference voltage. The reference can be as low as 100mV or can be tied directly to VCC. The noise level is 600nV RMS independent of VREF. This allows direct digitization of low level signals with 16bit accuracy. The LTC2482 includes an on-chip trimmed oscillator, eliminating the need for external crystals or oscillators and provides 87dB rejection of 50Hz and 60Hz line frequency noise. Absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent pending.
FEATURES

Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise, Independent of VREF Operates with a Reference as Low as 100mV with 16-Bit Resolution GND to VCC Input/Reference Common Mode Range Simultaneous 50Hz/60Hz Rejection Mode 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Total Unadjusted Error No Latency: Digital Filter Settles in a Single Cycle Single Supply 2.7V to 5.5V Operation Internal Oscillator Available in a Tiny (3mm x 3mm) 10-Lead DFN Package
APPLICATIO S

Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Strain Gauge Transducers Instrumentation Industrial Process Control DVMs and Meters
TYPICAL APPLICATIO
VCC
+FS Error vs RSOURCE at IN+ and IN-
VCC = 5V 60 VREF = 5V VIN+ = 3.75V VIN- = 1.25V 40 FO = GND 20 TA = 25C CIN = 1F 0 -20 -40
2482 TA01
80
10k SENSE 10k
IDIFF = 0 1F
VIN+
VREF LTC2482
VCC
SDO SCK CS 3-WIRE SPI INTERFACE
VIN- GND FO
+FS ERROR (ppm)
1F
-60 -80 1 10 100 1k RSOURCE () 10k 100k
2482 TA02
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LTC2482
ABSOLUTE
(Notes 1, 2)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW *GND 1 VCC 2 VREF 3 IN
+
Supply Voltage (VCC) to GND ...................... - 0.3V to 6V Analog Input Voltage to GND ....... - 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2482C ................................................... 0C to 70C LTC2482I ................................................ - 40C to 85C Storage Temperature Range ................ - 65C to 125C
10 FO 9 SCK 11 8 GND 7 SDO 6 CS
ORDER PART NUMBER LTC2482CDD LTC2482IDD
4
IN- 5
DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN
DD PART MARKING** LBSQ
TJMAX = 125C, JA = 43C/ W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB *PIN 1 MAY BE DRIVEN WITH A DIGITAL SIGNAL IN ORDER TO REMAIN PIN COMPATIBLE WITH THE LTC2480/LTC2484
Consult LTC Marketing for parts specified with wider operating temperature ranges. **The temperature grade is indicated by a label on the shipping container.
ELECTRICAL CHARACTERISTICS ( OR AL SPEED)
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1 VREF VCC, -FS VIN +FS (Note 5) 5V VCC 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V VREF VCC, GND IN+ = IN- VCC (Note 14) 2.5V VREF VCC , GND IN+ = IN- VCC 2.5V VREF VCC, IN+ = 0.75VREF, IN- = 0.25VREF 2.5V VREF VCC, IN+ = 0.75VREF, IN- = 0.25VREF 2.5V VREF VCC, IN+ = 0.75VREF, IN- = 0.25VREF 2.5V VREF VCC, IN+ = 0.75VREF, IN- = 0.25VREF 5V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V VCC 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. (Notes 3, 4)
MIN

TYP 2 1 0.5 10
MAX 20 5 32
UNITS Bits ppm of VREF ppm of VREF V nV/C ppm of VREF ppm of VREF/C
16
0.1
32 0.1 15
ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF ppm of VREF VRMS
Output Noise
5V VCC 5.5V, VREF = 5V, GND IN- = IN+ VCC (Note 13)
0.6
2
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LTC2482
CO VERTER CHARACTERISTICS
PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 50Hz 2% Input Common Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz 2% Input Normal Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz/60Hz 2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz 2% Power Supply Rejection, 60Hz 2% CONDITIONS 2.5V 2.5V
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
MIN

A ALOG I PUT A D REFERE CE The denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 3)
SYMBOL IN+ IN- FS LSB VIN VREF CS CS (IN+) (IN-) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN- Voltage Full Scale of the Differential Input (IN+ - IN-) Least Significant Bit of the Output Code Input Differential Voltage Range (IN+ - IN-) Reference Voltage Range IN+ IN- Sampling Capacitance Sampling Capacitance Sleep Mode, IN+ = GND Sleep Mode, IN- = GND Sleep Mode, VREF = VCC

CS (VREF) IDC_LEAK (IN+) IDC_LEAK (IN-) IDC_LEAK (VREF)
VREF Sampling Capacitance IN+ DC Leakage Current IN- DC Leakage Current VREF Leakage Current -10 -10 -100
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TYP
MAX
UNITS dB dB dB
VREF VCC, GND IN- = IN+ VCC (Note 5) VREF VCC, GND IN- = IN+ VCC (Note 5)
140 140 140 110 110 87 120 140 120 120 120 120 120
2.5V VREF VCC, GND IN- = IN+ VCC (Note 5) 2.5V VREF VCC, GND IN- = IN+ VCC (Notes 5, 7) 2.5V VREF VCC, GND IN- = IN+ VCC (Notes 5, 8) 2.5V VREF VCC, GND IN- = IN+ VCC (Notes 5, 9) 2.5V VREF VCC, GND IN- = IN+ VCC (Note 5) VREF = 2.5V, IN- = IN+ = GND VREF = 2.5V, IN- = IN+ = GND (Note 7) VREF = 2.5V, IN- = IN+ = GND (Note 8)
dB dB dB dB dB dB dB
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CONDITIONS
MIN GND - 0.3V GND - 0.3V 0.5VREF FS/216 -FS 0.1
TYP
MAX VCC + 0.3V VCC + 0.3V
UNITS V V V
+FS VCC 11 11 11 1 1 1 10 10 100
V V pF pF pF nA nA nA
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LTC2482
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO IO = -800A IO = 1.6mA IO = -800A IO = 1.6mA CONDITIONS 2.7V VCC 5.5V 2.7V VCC 5.5V
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
MIN

POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
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TYP
MAX
UNITS V
VCC - 0.5 0.5 VCC - 0.5 0.5 -10 -10 10 10 10 10
V V V A A pF pF V
2.7V VCC 5.5V (Note 10) 2.7V VCC 5.5V (Note 10) 0V VIN VCC 0V VIN VCC (Note 10)

VCC - 0.5 0.4 VCC - 0.5 0.4 -10 10
V V V A
MIN 2.7

TYP 160 1
MAX 5.5 250 2
UNITS V A A
Conversion Mode (Note 12) Sleep Mode (Note 12)
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LTC2482
TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV_1 fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time External SCK 24-Bit Data Output Time CS to SDO Low CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS (Note 15)

Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = 0.5VREF VIN = IN+ - IN-, VIN(CM) = (IN+ + IN-)/2 Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: fEOSC = 256kHz 2% (external oscillator). Note 8: fEOSC = 307.2kHz 2% (external oscillator).
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MIN 10 0.125 0.125 144.1
TYP
MAX 4000 100 100
UNITS kHz s s ms ms kHz kHz
Simultaneous 50Hz/60Hz External Oscillator Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 10) (Note 10) (Note 10) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 10)

146.9 149.9 41036/fEOSC (in kHz) 38.4 fEOSC/8

45 125 125 0.61
55 4000
% kHz ns ns
0.625 0.64 192/fEOSC (in kHz) 24/fESCK (in kHz) 200 200 200 200
ms ms ms ns ns ns ns ns ns ns
0 0 0 50 15 50
(Note 10) (Note 10) (Note 5)

50
ns
Note 9: Simultaneous 50Hz/60Hz rejection (internal oscillator) or fEOSC = 280kHz 2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK mode. In external SCK mode, the SCK pin is used as digital input and the driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital output and the output clock signal during the data output is fISCK. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: Refer to Applications Information section for performance vs data rate graphs.
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LTC2482 TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (VCC = 5V, VREF = 5V)
3 2
INL (ppm OF VREF)
VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND
INL (ppm OF VREF)
1 0
-45C
25C
1 -45C, 25C, 90C 0 -1 -2 -3 -1.25
INL (ppm OF VREF)
85C -1 -2 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 INPUT VOLTAGE (V)
Total Unadjusted Error (VCC = 5V, VREF = 5V)
12 8 VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 12 8 85C
TUE (ppm OF VREF)
TUE (ppm OF VREF)
4 0 -4 -8 -12 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) -45C
4 0 -4 -8 -12 -1.25 -45C
TUE (ppm OF VREF)
25C
Offset Error vs VIN(CM)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -1 0 1 3 2 VIN(CM) (V) 4 5 6
2482 G07
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
VCC = 5V VREF = 5V VIN = 0V TA = 25C
6
UW
2
2482 G01
Integral Nonlinearity (VCC = 5V, VREF = 2.5V)
3 2 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND
Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V)
3 2 1 -45C, 25C, 90C 0 -1 -2 -3 -1.25 VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND
2.5
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2482 G02
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2482 G03
Total Unadjusted Error (VCC = 5V, VREF = 2.5V)
VCC = 5V VREF = 5V VIN(CM) = 1.25V FO = GND 12 85C 25C 4 0 -4 -8 8
Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V)
VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND
25C
85C
-45C
2
2.5
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2482 G05
-12 -1.25
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2482 G06
2482 G04
Offset Error vs Temperature
0.3 0.2 0.1 0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND
-0.1 -0.2
-0.3 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
2482 G08
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LTC2482 TYPICAL PERFOR A CE CHARACTERISTICS
Offset Error vs VCC
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 2.7 REF VIN = 0V VIN(CM) = GND TA = 25C REF+ = 2.5V - = GND 0.3 0.2 0.1 0
OFFSET ERROR (ppm OF VREF)
3.1
3.5
3.9 4.3 VCC (V)
4.7
5.1
5.5
OFFSET ERROR (ppm OF VREF)
On-Chip Oscillator Frequency vs Temperature
310
310
308
FREQUENCY (kHz)
FREQUENCY (kHz)
306
304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND 0 15 30 45 60 TEMPERATURE (C) 75 90
302
300 -45 -30 -15
PSRR vs Frequency at VCC
0 -20 -40
REJECTION (dB)
-60 -80 -100 -120 -140 0 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M
REJECTION (dB)
VCC = 4.1V DC VREF = 2.5V IN+ = GND IN- = GND FO = GND TA = 25C
UW
Offset Error vs VREF
VCC = 5V REF- = GND VIN = 0V VIN(CM) = GND TA = 25C
-0.1 -0.2
-0.3 0 1 2 3 VREF (V) 4 5
2482 G10
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On-Chip Oscillator Frequency vs VCC
VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND
308
306
304
302
300
2.5
3.0
3.5
4.0 VCC (V)
4.5
5.0
5.5
2482 G12
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PSRR vs Frequency at VCC
0 -20 -40 -60 -80 -100 -120 -140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz)
2482 G14
VCC = 4.1V DC 1.4V VREF = 2.5V IN+ = GND IN- = GND FO = GND TA = 25C
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LTC2482 TYPICAL PERFOR A CE CHARACTERISTICS
PSRR vs Frequency at VCC
VCC = 4.1V DC 0.7V VREF = 2.5V -20 IN+ = GND IN- = GND -40 FO = GND TA = 25C -60 -80 -100 -120 -140 30600
100 -45 -30 -15
0
CONVERSION CURRENT (A)
REJECTION (dB)
30650
30750 FREQUENCY AT VCC (Hz)
Sleep Mode Current vs Temperature
2.0
500 450 SUPPLY CURRENT (A)
SLEEP MODE CURRENT (A)
FO = GND 1.8 CS = VCC SCK = NC 1.6 SDO = NC 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 VCC = 2.7V VCC = 5V
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30700
Conversion Current vs Temperature
200 FO = GND CS = GND SCK = NC SDO = NC VCC = 5V 160 VCC = 2.7V
180
140
120
30800
2482 G15
0 15 30 45 60 TEMPERATURE (C)
75
90
2482 G16
Conversion Current vs Data Output Rate
VREF = VCC IN+ = GND IN- = GND 400 SCK = NC SDO = NC 350 CS = GND FO = EXT OSC TA = 25C 300 250 200 150 100 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2482 G18
VCC = 5V
VCC = 3V
2482 G17
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LTC2482
PI FU CTIO S
GND (Pin 1): Ground. This pin should be tied to ground; however, in order to remain pin compatible with the LTC2480/LTC2484, this pin may be driven HIGH or LOW. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. VREF (Pin 3): Positive Reference Input. The voltage on this pin can have any value between 0.1V and VCC. The negative reference input is GND (Pin 8). IN+ (Pin 4), IN- (Pin 5): Differential Analog Inputs. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ - IN-) extends from - 0.5 * VREF to 0.5 * VREF. Outside this input range the converter produces unique overrange and underrange output codes. CS (Pin 6): Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 7): Three-State Digital Output. During the Data Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. GND (Pin 8): Ground. Shared pin for analog ground, digital ground and reference ground. Should be connected directly to a ground plane through a minimum impedance. SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 10): Frequency Control Pin. Digital input that controls the conversion clock. When FO is connected to GND the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate or the digital filter rejection null. Exposed Pad (Pin 11): This pin is ground and should be soldered to the PCB, GND plane. For prototyping purposes this pin may remain floating.
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LTC2482
FU CTIO AL BLOCK DIAGRA
3 VREF
4
IN+
5
IN -
GND 8
TEST CIRCUITS
VCC 1.69k
SDO 1.69k CLOAD = 20pF
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
2482 TC01
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2 VCC GND 1 IN
+
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REF+ 3RD ORDER ADC SERIAL INTERFACE
SCK SD0 CS
9 7 6
IN
-
REF -
AUTOCALIBRATION AND CONTROL
FO
10
INTERNAL OSCILLATOR
2482 FD
SDO CLOAD = 20pF
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
2482 TC02
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LTC2482
TI I G DIAGRA S
Timing Diagram Using Internal SCK
CS t1 SDO t3 SCK SLEEP DATA OUT CONVERSION
2482 TD1
CS t1 SDO t5 SCK SLEEP t6 t4 DATA OUT CONVERSION
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION Converter Operation Cycle
The LTC2482 is a low power, delta-sigma analog-todigital converter with an easy to use 3-wire serial interface and automatic differential input current cancellation. Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2482 performs a conversion. Once the conversion is complete, the device enters the sleep state.
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t2
tKQMIN
tKQMAX
Timing Diagram Using External SCK
t2
tKQMIN
tKQMAX
CONVERT
SLEEP
FALSE
CS = LOW AND SCK TRUE
DATA OUTPUT
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Figure 1. LTC2482 State Transition Diagram
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LTC2482
APPLICATIO S I FOR ATIO
While in this sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device exits the low power mode and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains LOW after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this point will terminate the data output state and start a new conversion. The conversion result is shifted out of the device through the serial data output pin (SDO) on the falling edge of the serial clock (SCK) (see Figure 2). Through timing control of the CS and SCK pins, the LTC2482 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Easy Drive Input Current Cancellation The LTC2482 combines a high precision delta-sigma ADC with an automatic differential input current cancellation front end. A proprietary front-end passive sampling network transparently removes the differential input cur-
CS BIT 23 SDO Hi-Z EOC BIT 22 DMY BIT 21 SIG BIT 20 MSB BIT 19 B16 CONVERSION RESULT BIT 18 BIT 4 LSB BIT 3 BIT 2 BIT 1 BIT 0
SCK
SLEEP
Figure 2. Output Data Timing
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rent. This enables external RC networks and high impedance sensors to directly interface to the LTC2482 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Input Current Cancellation section). This unique architecture does not require on-chip buffers enabling input signals to swing all the way to ground and up to VCC. Furthermore, the cancellation does not interfere with the transparent offset and full-scale autocalibration and the absolute accuracy (full scale + offset + linearity) is maintained with external RC networks. Output Data Format The LTC2482 serial output data stream is 24 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 17 bits are the conversion result, MSB first. The remaining 4 bits are always zero. Bit 21 and Bit 20 together are also used to indicate an underrange condition (the differential input voltage is below -FS) or an overrange condition (the differential input voltage is above +FS). In applications where a processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the LTC2482's digital interface will ignore extra clock edges seen during the next conversion period after the 24th and output "1" for the extra clock cycles. Furthermore, CS may be pulled high prior to outputting all 24 bits, aborting the data out transfer and initiating a new conversion.
DATA OUTPUT CONVERSION
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LTC2482
APPLICATIO S I FOR ATIO
Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. Bit 20 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 21 also provides the underrange or overrange indication. If both Bit 21 and Bit 20 are HIGH, the differential input voltage is above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below -FS. The function of these bits is summarized in Table 1.
Table 1. LTC2482 Status Bits
INPUT RANGE VIN 0.5 * VREF 0V VIN < 0.5 * VREF -0.5 * VREF VIN < 0V VIN < - 0.5 * VREF BIT 23 BIT 22 BIT 21 BIT 20 EOC DMY SIG MSB 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
Bits 20-4 are the 16-bit plus sign conversion result MSB first. Bits 3-0 are always low and are included to maintain software compatibility with the LTC2480.
Table 2. LTC2482 Output Data Format
DIFFERENTIAL INPUT VOLTAGE VIN * VIN* FS** FS** - 1LSB 0.5 * FS** 0.5 * FS** - 1LSB 0 -1LSB - 0.5 * FS** - 0.5 * FS** - 1LSB - FS** VIN* < -FS** BIT 23 EOC 0 0 0 0 0 0 0 0 0 0 BIT 22 DMY 0 0 0 0 0 0 0 0 0 0 BIT 21 SIG 1 1 1 1 1 0 0 0 0 0
*The differential input voltage VIN = IN+ - IN-. **The full-scale voltage FS = 0.5 * VREF.
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Data is shifted out of the SDO pin under control of the serial clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes in real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 23) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN- pins is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from -FS = -0.5 * VREF to +FS = 0.5 * VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value corresponding to -FS - 1LSB.
BIT 20 MSB 1 0 0 0 0 1 1 1 1 0 BIT 19 0 1 1 0 0 1 1 0 0 1 BIT 18 0 1 0 1 0 1 0 1 0 1 BIT 17 0 1 0 1 0 1 0 1 0 1 ... ... ... ... ... ... ... ... ... ... ... BIT 4 0 1 0 1 0 1 0 1 0 1 BITS 3-0 0 0 0 0 0 0 0 0 0 0
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LTC2482
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Conversion Clock
NORMAL MODE REJECTION (dB)
A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a SINC or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2482 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Frequency Rejection Selection (FO) The LTC2482 internal oscillator provides better than 87dB normal mode rejection at the line frequency and all its harmonics (up to the 255th) for the frequency range 48Hz to 62.4Hz. When a fundamental rejection frequency different from 50Hz/ 60Hz is required, when more than 87dB rejection is needed for 50Hz/60Hz, or when the converter must be synchronized with an outside source, the LTC2482 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 10kHz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2482 provides better than 110dB
Table 3. LTC2482 State Duration
STATE CONVERT OPERATING MODE Internal Oscillator External Oscillator 50Hz/60Hz Rejection
FO = External Oscillator with Frequency fEOSC kHz (fEOSC/5120 Rejection) FO = LOW/HIGH (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz
SLEEP DATA OUTPUT Internal Serial Clock
External Serial Clock with Frequency fSCK kHz
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normal mode rejection in a frequency range of fEOSC/5120 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/5120 is shown in Figure 3.
-80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -12 -8 -4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
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Figure 3. LTC2482 Normal Mode Rejection When Using an External Oscillator
Whenever an external clock is not present at the FO pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2482 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 3 summarizes the duration of each state and the achievable output data rate as a function of FO.
DURATION 147ms, Output Data Rate 6.8 Readings/s 41036/fEOSCs, Output Data Rate fEOSC/41036 Readings/s
As Long As CS = HIGH, After a Conversion is Complete As Long As CS = LOW But Not Longer Than 0.62ms (24 SCK Cycles) As Long As CS = LOW But Not Longer Than 192/fEOSCms (24 SCK Cycles) As Long As CS = LOW But Not Longer Than 24/fSCKms (24 SCK Cycles)
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Ease of Use
The LTC2482 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. The LTC2482 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2482 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. Following the POR signal, the LTC2482 starts a normal conversion cycle and follows the succession of states described in Figure 1. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range The LTC2482 external reference voltage range is 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. Since the transition noise (600nV) is much less than the quantization noise (VREF/217), a decrease in the refer-
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ence voltage will increase the converter resolution. A reduced reference voltage will improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates (see the Output Data Rate section). The negative reference input to the converter is internally tied to GND. GND (Pin 8) should be connected to a ground plane through as short a trace as possible to minimize voltage drop. The LTC2482 has an average operational current of 160A and for 1 parasitic resistance, the voltage drop of 160V causes a gain error of 2LSB for VREF = 5V. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN- input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2482 converts bipolar differential input signal, VIN = IN+ - IN-, from - FS to +FS where FS = 0.5 * VREF. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Since the differential input current cancellation does not rely on an on-chip buffer, current cancellation as well as DC performance is maintained rail-to-rail. Input signals applied to IN+ and IN- pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN- pins without affecting the performance of the devices. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency.
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LTC2482
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SERIAL INTERFACE TIMING MODES
The LTC2482's 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle or continuous conversion. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 4. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete.
Table 4. LTC2482 Interface Timing Modes
SCK SOURCE External External Internal Internal
CONFIGURATION External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion
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When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. The output data is shifted out of the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. In applications where the processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the LTC2482's digital interface will ignore extra clock edges seen during the next conversion period after the 24th and outputs "1" for the extra clock cycles. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 24th falling edge of SCK (see Figure 5). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.
CONVERSION CYCLE CONTROL CS and SCK SCK CS Continuous DATA OUTPUT CONTROL CS and SCK SCK CS Internal CONNECTION and WAVEFORMS Figures 4, 5 Figure 6 Figures 7, 8 Figure 9
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LTC2482
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REFERENCE VOLTAGE 0.1V TO VCC
TEST EOC (OPTIONAL)
ANALOG INPUT
CS TEST EOC SDO Hi-Z SCK (EXTERNAL) CONVERSION SLEEP SLEEP DATA OUTPUT CONVERSION
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BIT 23 EOC Hi-Z
BIT 22
BIT 21 SIG
Figure 4. External Serial Clock, Single Cycle Operation
TEST EOC (OPTIONAL)
CS TEST EOC TEST EOC
BIT 0 SDO EOC
BIT 23 EOC
BIT 22
Hi-Z
Hi-Z
Hi-Z
SCK (EXTERNAL) SLEEP CONVERSION SLEEP SLEEP DATA OUTPUT CONVERSION
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DATA OUTPUT
Figure 5. External Serial Clock, Reduced Data Output Length
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2.7V TO 5.5V 1F 2 VCC LTC2482 3 VREF SCK SDO 4 5 IN+ IN- CS GND 7 6 8,1 9 3-WIRE SPI INTERFACE FO 10 INT/EXT CLOCK BIT 20 MSB BIT 19 BIT 18 BIT 17 BIT 16 BIT 4 LSB Hi-Z BIT 0 TEST EOC
2.7V TO 5.5V 1F 2 VCC LTC2482 REFERENCE VOLTAGE 0.1V TO VCC 3 VREF SCK SDO 4 ANALOG INPUT 5 IN+ IN- CS GND 7 6 8,1 9 3-WIRE SPI INTERFACE FO 10 INT/EXT CLOCK BIT 21 SIG BIT 20 MSB Hi-Z BIT 19 BIT 18 BIT 17 BIT 16 BIT 9 BIT 8
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External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal (see Figure 6). CS may be permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded typically 4ms after VCC exceeds approximately 2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion ends. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. The output data is shifted out of the SDO pin on each falling edge of SCK. EOC can be latched on the first rising edge of SCK. On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. In applications where the processor generates
CS
BIT 23 SDO EOC
BIT 22
BIT 21 SIG
SCK (EXTERNAL) CONVERSION DATA OUTPUT CONVERSION
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Figure 6. External Serial Clock, CS = 0 Operation
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32 clock cycles, or to remain compatible with higher resolution converters, the LTC2482's digital interface will ignore extra clock edges seen during the next conversion period after the 24th and outputs "1" for the extra clock cycles. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle (see Figure 7). In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state.
2.7V TO 5.5V 1F 2 VCC LTC2482 REFERENCE VOLTAGE 0.1V TO VCC 3 VREF SCK SDO 4 ANALOG INPUT 5 IN+ IN- CS GND 7 6 8,1 9 2-WIRE SPI INTERFACE FO 10 INT/EXT CLOCK BIT 20 MSB BIT 19 BIT 18 BIT 17 BIT 16 BIT 4 LSB
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When testing EOC, if the conversion is complete (EOC = 0), the device will exit the low power mode during the EOC test. In order to allow the device to return to the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 12s if the device is using its internal oscillator. If FO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC in seconds. If CS is pulled HIGH before time tEOCtest, the device returns to the sleep state and the conversion result is held in the internal static shift register. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data I/O cycle concludes after the 24th rising edge. The output data is shifted out of the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts.
2.7V TO 5.5V 1F 2
TEST EOC BIT 23 SDO Hi-Z Hi-Z EOC
BIT 22
BIT 21 SIG
BIT 20 MSB
SCK (INTERNAL) CONVERSION SLEEP SLEEP DATA OUTPUT CONVERSION
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Figure 7. Internal Serial Clock, Single Cycle Operation
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Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 24th rising edge of SCK (see Figure 8). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2482's internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2482's internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode.
VCC LTC2482 REFERENCE VOLTAGE 0.1V TO VCC 3 VREF SCK SDO 4 ANALOG INPUT 5 IN
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FO
10
INT/EXT CLOCK VCC 10k
9 7 6 8,1 3-WIRE SPI INTERFACE
CS GND
IN-
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4 LSB
BIT 0
TEST EOC
Hi-Z
Hi-Z
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A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire (output only) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal (see Figure 9). CS may be permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 2V. An internal weak
TEST EOC (OPTIONAL) > tEOCtest CS TEST EOC BIT 0 SDO Hi-Z EOC Hi-Z
BIT 23 EOC Hi-Z Hi-Z
BIT 22
SCK (INTERNAL) SLEEP DATA OUTPUT CONVERSION SLEEP SLEEP DATA OUTPUT CONVERSION
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Figure 8. Internal Serial Clock, Reduce Data Output Length
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pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data input/ output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. The output data is shifted out of the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.
2.7V TO 5.5V 1F 2 VCC LTC2482 REFERENCE VOLTAGE 0.1V TO VCC 3 VREF SCK SDO 4 ANALOG INPUT 5 IN+ IN- CS GND 7 6 8,1 9 3-WIRE SPI INTERFACE FO 10 INT/EXT CLOCK VCC 10k BIT 21 SIG BIT 20 MSB Hi-Z BIT 19 BIT 18 BIT 17 BIT 16 BIT 8 TEST EOC
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LTC2482
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CS SDO BIT 23 EOC BIT 22 BIT 21 SIG BIT 20 MSB BIT 19 BIT 18 BIT 17 BIT 16 BIT 4 LSB BIT 0
SCK (INTERNAL) CONVERSION DATA OUTPUT CONVERSION
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Figure 9. Internal Serial Clock, CS = 0 Continuous Operation
PRESERVING THE CONVERTER ACCURACY The LTC2482 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are required. Digital Signal Levels The LTC2482's digital interface is easy to use. Its digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard CMOS logic levels and the internal hysteresis receivers can tolerate edge transition times as slow as 100s. However, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. While a digital input signal is in the range 0.5V to (VCC - 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the power supply current may increase even if the signal in question is at a valid logic level.
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2.7V TO 5.5V 1F 2 VCC LTC2482 REFERENCE VOLTAGE 0.1V TO VCC 3 VREF SCK SDO 4 ANALOG INPUT 5 IN+ IN- CS GND 7 6 8,1 9 2-WIRE SPI INTERFACE FO 10 INT/EXT CLOCK VCC 10k
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For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC - 0.4V)]. During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the pins can severely disturb the analog to digital conversion process. Undershoot and overshoot occur because of the impedance mismatch of the circuit board trace at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to the LTC2482. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2482 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver output pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology.
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An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The differential input architecture reduces the converter's sensitivity to ground currents. Particular attention must be given to the connection of the FO signal when the LTC2482 is used with an external conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals can result in DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals can result in a DC offset error. Such perturbations can occur due to asymmetric capacitive coupling between the FO signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum
IREF+ VREF + ILEAK IIN+ VIN+ ILEAK IIN- VIN- ILEAK IREF- GND ILEAK SWITCHING FREQUENCY fSW = 123kHz INTERNAL OSCILLATOR fSW = 0.4 * fEOSC EXTERNAL OSCILLATOR VCC ILEAK RSW (TYP) 10k
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VCC ILEAK RSW (TYP) 10k
I IN+ VCC ILEAK RSW (TYP) 10k CEQ 12pF (TYP) RSW (TYP) 10k
()
I REF +
()
where: V + VREFCM = REF 2 VIN = IN+ - IN- IN+ + IN- VINCM = 2 REQ = 2.98M INTERNAL OSCILLATOR REQ = 0.915 * 1012 / f EOSC EXTERNAL OSCILLATOR DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT WHERE REF- IS INTERNALLY TIED TO GND
VCC ILEAK
Figure 10. LTC2482 Equivalent Analog Input Circuit
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the loop area for the FO signal as well as the loop area for the differential input and reference connections. Even when F0 is not driven, other nearby signals pose similar EMI threats which will be minimized by following good layout practices. Driving the Input and Reference The input and reference pins of the LTC2482 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 10. For a simple approximation, the source impedance RS driving an analog input pin (IN+, IN-, VREF+ or GND) can be considered to form, together with RSW and CEQ (see Figure 10), a first order passive network with a time constant = (RS + RSW) * CEQ. The converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worstcase circumstances, the errors may add.
AVG
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= I IN -
()
AVG
=
VIN(CM) - VREF(CM) 0.5 * REQ
AVG
2 VIN 2 1.5 * VREF - VINCM + VREFCM 0.5 * VREF * DT 1.5VREF + VREF(CM) - VIN(CM) VIN - - - = 0.5 * REQ 0.5 * REQ VREF * REQ REQ VREF * REQ
(
)
(
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LTC2482
APPLICATIO S I FOR ATIO
When using the internal oscillator, the LTC2482's frontend switched-capacitor network is clocked at 123kHz corresponding to an 8.1s sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 8.1s/14 = 580ns. When an external oscillator of frequency fEOSC is used, the sampling period is 2.5/fEOSC and, for a settling error of less than 1ppm, 0.178/fEOSC. Automatic Differential Input Current Cancellation In applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001F bypass), complete settling of the input occurs. In this case, no errors are introduced and direct digitization of the sensor is possible. For many applications, the sensor output impedance combined with external bypass capacitors produces RC time constants much greater than the 580ns required for 1ppm accuracy. For example, a 10k bridge driving a 0.1F bypass capacitor has a time constant an order of magnitude greater than the required maximum. Historically, settling issues were solved using buffers. These buffers led to increased noise, reduced DC performance (Offset/Drift), limited input/output swing (cannot digitize signals near ground or VCC), added system cost and increased power. The LTC2482 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. This allows accurate direct digitization of high impedance sensors without the need for buffers. Additional errors resulting from mismatched leakage currents must also be taken into account. The switching algorithm forces the average input current on the positive input (IIN+) to be equal to the average input current on the negative input (IIN-). Over the complete conversion cycle, the average differential input current (IIN+ - IIN-) is zero. While the differential input current is zero, the common mode input current (IIN++ IIN-)/2 is proportional to the difference between the common mode input voltage (VINCM) and the common mode reference voltage (VREFCM). In applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balance bridge type application, both the differential and common mode input current are zero. The
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accuracy of the converter is unaffected by settling errors. Mismatches in source impedances between IN+ and IN- also do not affect the accuracy. In applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between VINCM and VREFCM. For a reference common mode of 2.5V and an input common mode of 1.5V, the common mode input current is approximately 0.74A. This common mode input current has no effect on the accuracy if the external source impedances tied to IN+ and IN- are matched. Mismatches in these source impedances lead to a fixed offset error but do not affect the linearity or full-scale reading. A 1% mismatch in 1k source resistances leads to a 1LSB shift (74V) in offset voltage. In applications where the common mode input voltage varies as a function of input signal level (single-ended input, RTDs, half bridges, current sensors, etc.), the common mode input current varies proportionally with input voltage. For the case of balanced input impedances, the common mode input current effects are rejected by the large CMRR of the LTC2482 leading to little degradation in accuracy. Mismatches in source impedances lead to gain errors proportional to the difference between the common mode input voltage and the common mode reference voltage. 1% mismatches in 1k source resistances lead to gain worst-case gain errors on the order of 1LSB (for 1V differences in reference and input common mode voltage). Table 5 summarizes the effects of mismatched source impedance and differences in reference/input common mode voltages.
Table 5. Suggested Input Configuration for LTC2482
BALANCED INPUT RESISTANCES Constant CIN > 1nF at Both VIN(CM) - VREF(CM) IN+ and IN-. Can Take Large Source Resistance with Negligible Error UNBALANCED INPUT RESISTANCES CIN > 1nF at Both IN+ and IN-. Can Take Large Source Resistance. Unbalanced Resistance Results in an Offset Which Can be Calibrated Minimize IN+ and IN- Capacitors and Avoid Large Source Impedance (< 5k Recommended)
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Varying CIN > 1nF at Both IN+ VIN(CM) - VREF(CM) and IN-. Can Take Large Source Resistance with Negligible Error
23
LTC2482
APPLICATIO S I FOR ATIO
RSOURCE CPAR 20pF IN + CIN VINCM + 0.5VIN
LTC2482 RSOURCE CPAR 20pF
IN - CIN
2482 F11
VINCM - 0.5VIN
Figure 11. An RC Network at IN+ and IN-
+FS ERROR (ppm)
VCC = 5V 60 VREF = 5V VIN+ = 3.75V - 40 VIN = 1.25V FO = GND 20 TA = 25C 0 -20 -40 -60 -80 1 10
80
CIN = 0pF CIN = 100pF CIN = 1nF, 0.1F, 1F
1k RSOURCE ()
100
10k
100k
2482 F12
Figure 12. +FS Error vs RSOURCE at IN+ or IN-
-FS ERROR (ppm)
VCC = 5V 60 VREF = 5V VIN+ = 1.25V - 40 VIN = 3.75V FO = GND 20 TA = 25C 0 -20 -40 -60 -80 1 10
80
CIN = 1nF, 0.1F, 1F
CIN = 100pF CIN = 0pF
100 1k RSOURCE ()
10k
100k
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Figure 13. -FS Error vs RSOURCE at IN+ or IN-
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The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by IN+ and IN-, the expected drift of the dynamic current and offset will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (10nA max), results in a small offset shift. A 1k source resistance will create a 1V typical and 10V maximum offset voltage. Reference Current In a similar fashion, the LTC2482 samples the differential reference pins VREF+ and GND transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations. For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 1nF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. In the following discussion, it is assumed the input and reference common mode are the same. Using internal oscillator (50Hz/60Hz rejection), the differential refer2482f
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LTC2482
APPLICATIO S I FOR ATIO
ence resistance is 1.1M and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the VREF pin. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.33 * 1012/fEOSC and each ohm of source resistance driving the VREF pin will result in 1.53 * 10-6 * fEOSCppm gain error. The typical +FS and -FS errors for various combinations of source resistance seen by the VREF pin and external capacitance connected to that pin are shown in Figures 14-17. In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
90 80 70 +FS ERROR (ppm) 60 50 40 30 20 10 0 -10 0 10 1k 100 RSOURCE () 10k 100k
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-FS ERROR (ppm)
VCC = 5V VREF = 5V VIN+ = 3.75V VIN- = 1.25V FO = GND TA = 25C CREF = 0.01F CREF = 0.001F CREF = 100pF CREF = 0pF
Figure 14. +FS Error vs RSOURCE at VREF (Small CREF)
500
400
+FS ERROR (ppm)
300
CREF = 0.1F
-FS ERROR (ppm)
VCC = 5V VREF = 5V VIN+ = 3.75V VIN- = 1.25V FO = GND TA = 25C
CREF = 1F, 10F -100 CREF = 0.01F -200 CREF = 1F, 10F -300 VCC = 5V VREF = 5V VIN+ = 1.25V VIN- = 3.75V FO = GND TA = 25C 0 200 600 400 RSOURCE () CREF = 0.1F
200 CREF = 0.01F 100
0
0
200
600 400 RSOURCE ()
800
1000
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Figure 16. +FS Error vs RSOURCE at VREF (Large CREF)
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The INL is caused by the input dependent terms -VIN2/ (VREF * REQ) - (0.5 * VREF * DT)/REQ in the reference pin current as expressed in Figure 10. When using internal oscillator with 50Hz/60Hz rejection, every 100 of reference source resistance translates into about 0.61ppm additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 100 of source resistance driving VREF translates into about 1.99 * 10-6 * fEOSCppm additional INL error. Figure 18 shows the typical INL error due to the source resistance driving the VREF pin when large CREF values are used. The user is advised to minimize the source impedance driving the VREF pin.
10 0 -10 -20 -30 -40 -50 VCC = 5V -60 VREF = 5V V + = 1.25V -70 VIN- = 3.75V IN -80 FO = GND TA = 25C -90 10 0 CREF = 0.01F CREF = 0.001F CREF = 100pF CREF = 0pF 1k 100 RSOURCE () 10k 100k
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Figure 15. -FS Error vs RSOURCE at VREF (Small CREF)
0
-400
-500
800
1000
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Figure 17. -FS Error vs RSOURCE at VREF (Large CREF)
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LTC2482
APPLICATIO S I FOR ATIO
10 VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25C A 4 CREF = 10F 2 0 -2 -4 -6 -8 -10 - 0.5 - 0.3 0.1 - 0.1 VIN/VREF (V) 0.3 0.5
2482 F18
R = 1k
INL (ppm OF VREF)
R = 500 R = 100
Figure 18. INL vs Differential Input Voltage and Reference Source Resistance for CREF > 1F
In applications where the reference and input common mode voltages are different, extra errors are introduced. For every 1V of the reference and input common mode voltage difference (VREFCM - VINCM) and a 5V reference, each Ohm of reference source resistance introduces an extra (VREFCM - VINCM)/(VREF * REQ) full-scale gain error which is 0.067ppm when using the internal oscillator (50Hz/60Hz rejection). If an external clock is used, the corresponding extra gain error is 0.22 * 10-6 * fEOSCppm. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by VREF+ and GND, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a small gain error. A 100 source resistance will create a 0.05V typical and 0.5V maximum full-scale error.
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Output Data Rate When using its internal oscillator, the LTC2482 produces 6.8ps with a notch frequency of 55Hz, for simultaneous 50Hz/60Hz rejection. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2482 output data rate can be increased as desired. The duration of the conversion phase is 41036/ fEOSC. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2482's exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN- pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2482 typical performance can be inferred from Figures 12, 13, 14 and 15 in which the horizontal axis is scaled by 307200/fEOSC. Third, an increase in the frequency of the external oscillator above 1MHz (a more than 3x increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive
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LTC2482
APPLICATIO S I FOR ATIO
50 40 30 TA = 85C 20 10 0 TA = 25C -10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2482 F19
OFFSET ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK
Figure 19. Offset Error vs Output Data Rate and Temperature
0 -500
-FS ERROR (ppm OF VREF)
RESOLUTION (BITS)
-1000 TA = 25C TA = 85C -2000
-1500
-2500 -3000 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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-3500
Figure 21. -FS Error vs Output Data Rate and Temperature
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OFFSET ERROR (ppm OF VREF)
VIN(CM) = VREF(CM) VIN = 0V 15 FO = EXT CLOCK TA = 25C 10 VCC = VREF = 5V 5 0 -5 VCC = 5V, VREF = 2.5V RESOLUTION (BITS)
-10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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Figure 23. Offset Error vs Output Data Rate and Reference Voltage
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3500 3000 2500 TA = 85C 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK
TA = 25C
Figure 20. +FS Error vs Output Data Rate and Temperature
22
VIN(CM) = VREF(CM) VCC = VREF = 5V 20 FO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 18 16 TA = 25C
14 TA = 85C 12 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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Figure 22. Resolution (INLMAX 1LSB) vs Output Data Rate and Temperature
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VIN(CM) = VREF(CM) VIN = 0V - 20 REF = GND FO = EXT CLOCK TA = 25C 18 RES = LOG 2 (VREF/INLMAX) 16 VCC = VREF = 5V VCC = 5V, VREF = 2.5V
14 12 10
0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2482 F24
Figure 24. Resolution (INLMAX 1LSB) vs Output Data Rate and Reference Voltage
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LTC2482
APPLICATIO S I FOR ATIO
degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 19 to 24. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Input Bandwidth The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2482 input bandwidth. When the internal oscillator is used the 3dB input bandwidth is 3.3Hz. If an external conversion clock generator of frequency fEOSC is connected to the FO pin, the 3dB input bandwidth is 10.7 * 10-6 * fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2482 input bandwidth is shown in Figure 25. When an external oscillator of frequency f EOSC is used, the shape of the LTC2482 input bandwidth can be derived from Figure 25 in which the horizontal axis is scaled by fEOSC/307200.
0
INPUT SIGNAL ATTENUATION (dB)
INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz)
-1 -2 -3 -4 -5 -6
1 3 4 0 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
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Figure 25. Input Signal Bandwidth Using the Internal Oscillator
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The conversion noise (600nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 47nVHz for an infinite bandwidth source and 64nVHz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2482, the ADC input referred system noise calculation can be simplified by Figure 26. The noise of an amplifier driving the LTC2482 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 26, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni * freqi. The total system noise
100 10 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2482 F26
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Figure 26. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source
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LTC2482
APPLICATIO S I FOR ATIO
(referred to the LTC2482 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2482 internal noise, the noise of the IN + driving amplifier and the noise of the IN - driving amplifier. If the FO pin is driven by an external oscillator of frequency fEOSC, Figure 26 can still be used for noise calculation if the x-axis is scaled by fEOSC/307200. For large values of the ratio fEOSC/307200, the Figure 26 plot accuracy begins to decrease, but at the same time the LTC2482 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2482 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2482 allows external lowpass filtering without degrading the DC performance of the device. The SINC4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2482's autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 * fN = 2048
0
INPUT NORMAL MODE REJECTION (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fN
INPUT NORMAL MODE REJECTION (dB)
fN = fEOSC /5120
2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz)
8fN
2482 F27
Figure 27. Input Normal Mode Rejection at DC
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* fOUTMAX where fN is the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode with 50Hz/60Hz rejection, fS = 13960Hz. In the external oscillator mode, fS = fEOSC/20. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 27 (rejection near DC) and Figure 28 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value. The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figure 29. Typical measured values of the normal mode rejection of the LTC2482 operating with an internal oscillator (50Hz/60Hz rejection) is shown in Figure 29. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2482. If passive RC components are placed in front of the LTC2482, the input dynamic current should be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2482 allows external RC networks without significant degradation in DC performance. Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz)
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Figure 28. Input Normal Mode Rejection at fS = 256fN
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LTC2482
APPLICATIO S I FOR ATIO
0 NORMAL MODE REJECTION (dB) -20 -40 - 60 -80 -100 -120 MEASURED DATA CALCULATED DATA
0
20
40
60
80 100 120 140 INPUT FREQUENCY (Hz)
160
180
Figure 29. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale
proprietary architecture used for the LTC2482 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and the LTC2482 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2482 has a full-scale differential input range of 5V peak-to-peak. Remote Sensing with Easy Drive Input Current Cancellation One problem faced by designers of high performance data acquisition systems is achieving data sheet specified performance in a real world environment. One advantage delta sigma type ADCs offer over the alternatives is on-chip digital filtering (noise suppression). The disadvantage (solved by Easy Drive technology) is the drive requirements inherent in delta sigma ADC architectures. In order to demonstrate the full potential of the Easy Drive technology, a practical test case was characterized (see Figure 30). Precise measurements of offset, noise and linearity were measured under extreme test conditions. A remote sensor was digitized through 100 meters of cable applied to an RC network with low accuracy 1% resistors. A remote sensor voltage was swept from 0 to 2.5 with less than 1LSB linearity error (see Figure 31). Noise levels of 650nV RMS and offsets below 5V were measured (see Figure 32).
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VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25C
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Fundamentally, an oversampled data converter ( ADC) directly connected to a long cable and a low precision RC network leads to many problems greatly limiting the accuracy of the system. These include transmission line effects, noise and DC settling errors. The sampling network of ADCs injects high frequency current spikes into the cable. The resulting voltage spikes are reflected through the long wire and result in excessive noise and reduced accuracy. This problem is solved by placing a bypass capacitor across the input to the ADC. This capacitor serves as a charge reservoir for the ADC's sampling network and reduces the voltage spikes by the ratio of internal sampling capacitor to external bypass capacitor. A 1F bypass capacitor reduces the voltage spikes generated by the sampling network by a factor of 50,000 (1V spikes are reduced to 18V) and is sufficient to achieve data sheet specified noise and accuracy. The addition the large external bypass capacitor results in input settling errors. Typical 24-bit high resolution delta sigma ADCs sample at time intervals on the order of 10s. In order to fully settle with a 1F bypass capacitor, the source impedance must be lower than 1. Source impedances greater than 1 result in offset and full-scale errors due to the accumulation of charge settling errors over the complete conversion cycle. Easy Drive technology automatically removes the differential component of this error. The remaining common mode error is reduced to a fixed offset as a function of the external resistor matching seen at the plus and minus input of the ADC. In this extreme case, 1k external resistors with 1% matching result in a 3.5V offset while the linearity and noise are unaffected. The signal path contains a 100 meter wire connected to a low voltage source in a very noisy environment. Line frequency noise is rejected by the on chip digital filter and guaranteed by the high accuracy on chip oscillator. High frequency noise is rejected by the external lowpass filter formed by the input bypass capacitor and external resistors.
200
220
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LTC2482
PACKAGE DESCRIPTIO
3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 0.10 10
PIN 1 TOP MARK (SEE NOTE 5) 5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES) 1
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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DD Package 10-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 0.05 3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES)
(DD10) DFN 0403
0.25 0.05 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
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LTC2482
TYPICAL APPLICATIO
REMOTE SENSOR
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Figure 30. Differential Input Current Cancellation Enables Direct Digitization of Remote Sensors
5 4 3 2
INL (LSB)
NUMBER OF READINGS (%)
INTEGRAL NONLINEARITY THROUGH 100 METERS OF WIRE AND A 1k, 1F RC NETWORK
1 0 -1 -2 -3 -4 -5 0 0.5 1.5 1 INPUT VOLTAGE (V) 2 2.5
2482 F31
Figure 31. Input Current Cancellation Enables Precise DC Measurements Under Extreme Conditions
RELATED PARTS
PART NUMBER LTC1050 LT1236A-5 LT1460 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 DESCRIPTION Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference 24-Bit, No Latency ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ADCs in MSOP 4-/8-Channel, 24-Bit, No Latency ADCs with Differential Inputs 24-Bit, No Latency ADC with Differential Inputs COMMENTS No External Components 5V Offset, 1.6VP-P Noise 0.05% Max Initial Accuracy, 5ppm/C Drift 0.075% Max Initial Accuracy, 10ppm/C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.8VRMS Noise, 2ppm INL 1.45VRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200A 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 2.8V Noise, SSOP-16/MSOP Package 3ppm INL, Simultaneous 50Hz/60Hz Rejection 3.5kHz Output Rate, 200mV Noise, 24.6 ENOBs Pin Compatible with LTC2482 Pin Compatible with LTC2482
2482f LT/TP 0405 500 * PRINTED IN THE USA
LTC2411/LTC2411-1 24-Bit, No Latency ADCs with Differential Inputs in MSOP LTC2413 LTC2415/ LTC2415-1 LTC2414/LTC2418 LTC2420 LTC2430/LTC2431 LTC2440 LTC2480 LTC2484 24-Bit, No Latency ADC with Differential Inputs 24-Bit, No Latency ADCs with 15Hz Output Rate 8-/16-Channel 24-Bit, No Latency ADCs 20-Bit, No Latency ADC in SO-8 20-Bit, No Latency ADCs with Differential Inputs High Speed, Low Noise 24-Bit ADC 16-Bit, No Latency ADC with PGA and Temperature Sensor 16-Bit, No Latency ADC with Temperature Sensor
LTC2435/LTC2435-1 20-Bit, No Latency ADCs with 15Hz Output Rate
32
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
U
5V C8 1F 100 METERS 1k 1% 1F VIN- 1k 1% GND GND REF VCC C7 0.1F VIN+ LTC2482 CS SCK SDO FO
12 RMS NOISE = 630nV AVERAGE = -3.5V 10 2500 CONSECUTIVE READINGS 8 6 4 2 0 -5.25 -4.65 -4.05 -3.45 -2.85 -2.25 -1.65 2482 F32 OUTPUT READING (V)
Figure 32. Input Current Cancellation Enables Low Noise/ Low Offset Measurements under Extreme Conditions
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(c) LINEAR TECHNOLOGY CORPORATION 2005

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